16-Key Digital Piano

FPGA Project

Abstract

In this project, I created a 16-Key Digital Piano with similar functionality as a product for kids or can be scaled to a full-sized digital grand piano. With the limited amount of hardware available on the Blackboard, I was able to utilize all 16 switches and the analog headphone output to play piano keys. Mulitple keys can be played simultaneosly to play different scales. This project was implemented using Verilog on the Blackboard by Real Digital with the Xilinx XC7007S ZYNQ chip. The video above contains a short overview and demonstration of the project.

Introduction

There are 16 Keys which are the switches on the Blackboard that will enable each key to be played. The audio output is how the sound or key will be played on speakers or headphones. This project is implemented using Verilog which is a hardware development language.

Objectives

  1. Implement 16-Key Ditial Piano Using Verilog
  2. Create a testbench for the project to test for errors and functionality
  3. Add the constraints for the necessary pins on the Blackboard such as switches and audio output
  4. Program and demonstrate project on the Blackboard FPGA

Parts List

  • Blackboard by Real Digital alexander's profile picture
  • Headphones/Speakers
  • Hardware Design

    alexander's profile picture
    Figure 1: RTL Schematic for 16-Key Digital Piano

    The hardware design involves 3 inputs and 1 output. The three inputs is the switches which are the keys or in this case we call them notes, the other two are the clk and hush inputs. The clk input is necessary as we are going to use the clk frequency to generate the different frequencies for each note. The hush is a signal that will be used as a mute button to stop playing sound.

    From Figure 1, the blocks that I have impemented are shown. There registers and ROM that store that data needed to play the piano keys. The ROM is read-only memory which stores the counter limit values. These values are used to generate the frequency needed for each piano key or note. Below is the table of the counter limit values needed for each note. This is specific for a clk frequency of 100Mhz. There are also registers that store the value for the counter and counter limit. Also the speaker register, which stores the value for the speaker which is either high(1) or low(0). This is how the frequency for each note is generated.

    Table 1: Piano Key Half-Period Cycle counts

    The implementation consists of switching the counter limit depending on the note signal which will be connected to the switches in the constraint file. There will be a counter that used as a frequency divider with the 100Mhz clk as the reference. The counter counts up to the specific limit and keeps the speaker signal high or low until it reaches the limit and it will switch the speaker signal to high or low. This is how the PWM signal is generated to play each note. The speaker signal will be connected to the audio output on the Blackboard in the constraint file.

    Hardware Interface

    Constraints

    The XDC file also known as the the constraint file contains the pin assigments for the FPGA board. This is where I connect the signals from the design source to interface with the board. For this project, I use all 16 switches which is connected to the "note" signal which is 4 bits wide. I also need to connect the "speaker" signal to the audio output jack on the board in order to hear the sound. Last but not least, the clk and hush signals need to be connected as well. The "hush" signal will just be connected to a button.

    Testing & Techncial Challenges

    The testbench results are explained in the video above. However, the testbench consisted of testing out each note and analzying the output which was the speaker signal. I was able to compare the frequency of the speaker signal to Table 1 and each note matched almost identically.

    Conclusion

    I was able to succesfully implement and test my design using Verilog. I applied the knowledge I acquired from the courses I've taken in order to create a digital piano similar to the actual instrument and has the ability to play music with the correct keys played. This involved digital design including creating testbenches, design sources, and constraint files. I gained the knowledge of using the components on the FPGA board combined with digital design to create a saleable and functional product. This was a very fun FPGA project that opened my eye to other future project using the concepts from this project. I am confident in my abilites to impelement digital designs using Verilog after this project and from previous coursework.